1. Field of the Invention
The present invention relates to a semiconductor device suitably employed for a MOS-IC etc. as a single unit or with the incorporation of a power semiconductor device.
2. Related Arts
Recently, a vertical type power MOSFET has been used in many industrial fields for various features thereof such as high frequency characteristics, fast switching speed and low power driving.
As a conventional vertical type power MOSFET, there have been disclosed concave channel type DMOS structures in International Publication No. PCT WO93/03502 and the Japanese Unexamined Patent Publication No. 62-12167, for example. The proposed DMOS structure has a concave structure or a bathtub-shaped groove structure fabricated by a combination of local oxidation of silicon (LOCOS) technique and chemically etching off the formed thick oxide film (so-called LOCOS oxide film), which obtains the elimination of JFET resistance by means of the concave configuration thereof.
Furthermore, both publications disclose a formation of an initial groove which is conducted by means of wet etching and prior to the formation of the above-mentioned thick oxide film by means of LOCOS technique. The formation of the initial groove can improve productivity of the concave channel type DMOS structure. That is to say, if the concave configuration, the side surface of which becomes the channel part, is formed by LOCOS technique alone, the LOCOS oxidation time period would lengthen, and the angle of the groove side surface would be as gentle as approximately 30.degree., which would make it impossible to micronize cells and the reduction in the ON-resistance would not be promising. Furthermore, if the concave configuration is formed by the LOCOS technique alone, as the volume of Si almost doubles due to oxidation by nature, the channel part might be residually strained by the increase in the Si volume. Therefore, the etching process prior to the LOCOS oxidation, i.e., the initial groove formation process, is necessary by all means.